MOSFET I-V Characteristics MOSFET non-idealities Gerhard Klimeck [email protected] Klimeck –ECE606 Fall 2012 –notes adopted from Alam Outline 2 1) Square law/ simplified bulk charge theory 2) Velocity saturation in simplified theory 3) Few comments about bulk charge theory, small transistors 4) Flat band voltage - What is it and how to. Find many great new & used options and get the best deals for BULK Shindengen 20w60c-3 600v 20a Power MOSFET To-3p Ship at the best online prices at eBay! Free shipping for many products!Добавил:
4 IEEE TRANSACTIONS ON ELECTRON DEVICES
Comparison of (a) transverse stress proﬁles and (b) STI stress-induced hole mobility variations for planar versus trigate (WSTRIPE = 20 nm) bulk
MOSFETs using Taurus 3-D . The silicon stripe height is 10 nm for the trigate bulk MOSFETs, which provides for more uniform channel mobility because
of reduced STI-induced channel stress.
CESL-induced stress distribution in planar and trigate bulk MOSFETs. The CESL is assumed to be a 30-nm-thick silicon nitride with 2-GPa tensile
stress. LG = 20 nm, tox = 9 Å, gate electrode thickness (TGATE) = 40 nm, spacer width (LSPACER) = 20 nm, WSTRIPE = 20 nm, WSPACING = 20, and HSTRIPE = 10 nm.
132IV. IMPACT OF RANDOM VARIATIONS
133Here, LERand RDF-induced variations are compared for
134the three MOSFET structures. Gate LER proﬁles are sampled
135from a scanning electron micrograph of extreme ultraviolet
136resist lines. On average, these lines have an LER (3σ) value
of 4 nm and a line width roughness (LWR) value of 6.4 nm. 137 The distance between the consecutive sampling points of the 138 LER proﬁles is approximately 0.8 nm. Examples of simulated 139 structures with different gate LER proﬁles are shown in Fig. 8. 140 The source and drain junction proﬁles are assumed to have 141
SUN et al.: STUDY OF PLANAR MOSFET, SOI FinFET, AND TRIGATE MOSFET DESIGNS
Fig. 10. LERand RDFinduced variations in trigate bulk MOSFET, SOI
Fig. 8. Examples of simulated gate electrodes with different LER proﬁles.
FinFET, and planar bulk MOSFET.
LG = 20 nm, and tSi = 0.6 LG =
Fig. 9. LER-induced variation in trigate bulk MOSFET, SOI FinFET, and
planar bulk MOSFET. LG = 20 nm, and tSi = 0.6 LG = 12 nm.
142 the same LER as the gate electrode to simulate the worst case
143 scenario; thus, Le will have the same roughness proﬁle as
LG. The RDF proﬁles are generated using kinetic Monte Carlo
145 simulations  on the MOSFET structures with gate LER.
Three-dimensional device simulations are performed for the
147 optimized nominal designs to investigate the effects of LER
148 only and also to investigate the effects of LER, together with
RDF, in the source/drain and channel regions.
Fig. 9 shows the gate LER-induced VT variations (σVT )
151 for the SOI FinFET, planar bulk MOSFET, and trigate bulk
MOSFET with tSi = 0.6 LG. The variation is smallest for the
153 trigate bulk MOSFET design due to its superior electrostatic
154 integrity. The SOI FinFET has VT variation comparable to that
155 of the planar bulk MOSFET. This is because the two sidewall
156 gates of the FinFET have discrete different gate lengths due to
Fig. 11. Effect of tSi on LERand RDFinduced variations. LG = 20 nm.
gate LWR, whereas the effects of gate LWR on planar bulk
MOSFETs are somewhat averaged across the channel width.
(a) tSi = 0.6 LG = 12 nm. (b) tSi = 0.8 LG = 16 nm.
VT variations due to the presence of both LER and RDF are
160 shown in Fig. 10. VT lowering (where
VT is equal to the
gradient regions increases with smaller WSTRIPE  and 167
VT value of the nominal design subtracted by the mean VT
also because of larger LER-induced variation, the SOI FinFET 168
162 value of the MOSFET structures with gate LER and RDF)
does not provide for reduced random variation, as compared 169
163 is smallest for the trigate bulk MOSFET due to its superior
with the trigate bulk MOSFET design, although there are no 170
164 electrostatic integrity. Overall, the trigate bulk MOSFET also
channel dopants in the SOI FinFET. Fig. 11 shows the effect 171
165 shows comparable random VT
variation as the SOI FinFET.
of tSi on the random variation. For the trigate bulk MOSFET, 172
Because VT variation induced
in the source/drain
tSi = 0.6 LG yields the smallest random variation, whereas 173
174 for the planar bulk MOSFET, tSi = 0.8 LG is beneﬁcial for 175 reduced RDF-induced variability since the average number of 176 channel dopants is smaller.
178The impact of process-induced systematic and random vari-
179ations on transistor performance has been investigated for three
180different transistor structures. As compared with the planar bulk
181MOSFET and SOI FinFET, the trigate bulk MOSFET design
Mosfet Bulk Substrate
182shows the least variability and the best nominal performance.
183Thus, it is a promising device architecture for transistor scaling
184to the end of the technology roadmap.
IEEE TRANSACTIONS ON ELECTRON DEVICES
 X. Sun and T.-J. King Liu, “Scale length assessment of the tri-gate 206 bulk MOSFET design,” IEEE Trans. Electron Devices, vol. 56, no. 11, 207
pp. 2840–2842, Nov. 2009.
 A. Hokazono, H. Itokawa, N. Kusunoki, I. Mizushima,
S. Inaba, 209
S. Kawanaka, and Y. Toyoshima, “Steep channel & halo proﬁles utilizing 210 boron-diffusion-barrier layers (Si:C) for 32 nm node and beyond,” in VLSI 211
Symp. Tech. Dig., 2008, pp. 112–113.
 Synopsys, Inc., Mountain View, CA, Sentaurus User’s Manual, 2009.06, 213 2009. 214
G. Scott, J. Lutze, M. Rubin, F. Nouri, and M. Manley, “NMOS drive 215 current reduction caused by transistor layout and trench isolation induced 216
Mosfet Bulk Current
stress,” in IEDM Tech. Dig., 1999, pp. 827–830.
 Taurus User’s Manual, Synopsys, Inc., Mountain View, CA.
V. Varadarajan, L. Smith, S. Balasubramanian, and T.-J. King Liu, “Multi219 gate FET design for tolerance to statistical dopant ﬂuctuations,” in 220
Proc. IEEE Silicon Nanoelectron. Workshop, 2006, pp. 137–138.
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Xin Sun, photograph and biography not available at the time of publication. 222
186 H. Masuda, S. Ohkawa, A. Kurokawa, and M. Aoki, “Challenge:
187Variability characterization and modeling for 65to 90-nm process,” in
Proc. Custom Integr. Circuits Conf., 2005, pp. 593–599.
Victor Moroz, photograph and biography not available
at the time of 223
A. Asenov, A. R. Brown, J. H. Davies, S. Kaya, and G. Slavcheva,
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nanometer-scale MOSFETs,” IEEE Trans. Electron Devices, vol. 50,
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bulk to SOI to bulk,” IEEE Trans. Electron Devices, vol. 39, no. 7,
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D. J. Frank, Y. Taur, and H.-S. P. Wong, “Generalized scale length for
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X. Sun, Q. Lu, V. Moroz, H. Takeuchi, G. Gebara, J. Wetzel, S. Ikeda,
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no. 5, pp. 491–493, May 2008.
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